Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 3/28/2022
Document Table of Contents Data Realignment Block (Bit Slip)

Skew in transmitted data and skew added by the link cause channel-to-channel skew on the received serial data streams. If you enable the DPA, the received data is captured with different clock phases on each channel. This difference may cause misalignment of the received data from channel to channel. To compensate for this channel-to-channel skew and establish the correct received word boundary at each channel, each receiver channel has a dedicated data realignment circuit that realigns the data by inserting bit latencies into the serial stream.

An optional rx_bitslip_ctrl port controls the bit insertion of each receiver independently controlled from the internal logic. The data slips one bit on the rising edge of rx_bitslip_ctrl. The requirements for the rx_bitslip_ctrl signal include the following items:

  • The minimum pulse width is one period of the parallel clock in the logic array.
  • The minimum low time between pulses is one period of the parallel clock.
  • The signal is an edge-triggered signal.
  • The valid data is available four parallel clock cycles after the rising edge of rx_bitslip_ctrl.
Figure 10. Data Realignment TimingThis figure shows receiver output (rx_out) after one bit slip pulse with the deserialization factor set to 4.

The data realignment circuit has a bit slip rollover value set to the deserialization factor. An optional status port, rx_bitslip_max, is available to the FPGA fabric from each channel to indicate the reaching of the preset rollover point.

Figure 11. Receiver Data Realignment RolloverThis figure shows a preset value of four bit cycles before rollover occurs. The rx_bitslip_max signal pulses for one rx_coreclock cycle to indicate that rollover has occurred.

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