Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 3/28/2022
Public
Document Table of Contents

4.4. LVDS SERDES Intel® FPGA IP Design Examples

The LVDS SERDES IP can generate several design examples that match your IP configuration in the parameter editor. You can use these design examples as references for instantiating the IP core and the expected behavior in simulations.

You can generate the design examples from the LVDS SERDES IP parameter editor. After you have set the parameters that you want, click Generate Example Design. The IP generates the design example source files in the directory you specify.

Figure 36. Source Files in the Generated Design Example Directory


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