Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 11/30/2022
Document Table of Contents
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4.3.5. Guideline: Use Clock Phase Alignment Block to Improve Timing Closure

For large clock networks, skew added to the core clock through the clock network can affect timing closure. To improve timing closure between the periphery and the core, turn on the Use the CPA block for improved periphery-core timing feature.