Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 3/28/2022
Public
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3.1.6.3. PLLs Driving DPA-Enabled Differential Receiver and Transmitter Channels in LVDS Interface Spanning Multiple I/O Banks

If you use both differential transmitter and DPA-enabled receiver channels in a bank, the PLL can drive the transmitters spanning multiple adjacent I/O banks, but only the receivers in its own I/O bank.
Figure 21. PLLs Driving DPA-Enabled Differential Receiver and Transmitter Channels Across I/O Banks


Figure 22. Sharing Reference Clock Source to Differential Receiver and Transmitter Channels Across I/O Banks


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