4.1.3. LVDS SERDES IP Core Functional Modes
In the transmitter mode, the SERDES block acts as a serializer.
A PLL generates the following signals:
In the RX non-DPA mode, The SERDES block acts as a deserializer that bypasses the DPA and DPA-FIFO.
A PLL generates the fast_clock signal. Because the incoming data is captured at the bitslip with the fast_clock signal, you must ensure the correct clock–data alignment.
In the RX DPA-FIFO mode, the SERDES block acts as a deserializer that uses the DPA block.
The DPA block uses a set of eight DPA clocks to select the optimal phase for sampling data. These DPA clocks run at the fast_clock frequency with each clock phase-shifted 45° apart. The DPA-FIFO, a circular buffer, samples the incoming data with the selected DPA clock and forwards the data to LVDS clock domain. The bitslip circuitry then samples the data and inserts latencies to realign the data to match the desired word boundary of the deserialized data.
In the RX soft-CDR mode, the IP core forwards the optimal DPA clock (DPACLK) into the LVDS clock domain as the fast_clock signal. The IP core forwards the rx_divfwdclk, produced by the local clock generator, to the core through a PCLK network.
Because you must place RX interfaces in one I/O bank and each bank has only 12 PCLK resources, there are only 12 soft-CDR channels available.
To find out which pin pairs can support soft-CDR channels in each bank, refer to the device pin out file. In the device pin out file, the "Dedicated Tx/Rx Channel" column lists the available LVDS pin pairs in a LVDS<bank number>_<pin pair> <p or n> format. If the value of <pin pair> is an even number, the pin pair supports soft-CDR mode.
In the duplex mode, the IP core automatically enables the transmitters. You can select the receiver mode to use. The number of transmitters and receivers are the same.
The duplex mode allows the IP core to place receivers and transmitters in the same I/O bank. You can enable up to 11 transmitter and 11 receiver channels.
If you enable the duplex mode, the external PLL mode is disabled.