Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 3/28/2022
Public
Document Table of Contents

2.5.2.3. Soft-CDR Mode

The Intel® Stratix® 10 LVDS channel offers the soft-CDR mode to support the GbE and SGMII protocols. A receiver PLL uses the local clock source for reference.

Figure 15. Receiver Datapath in Soft-CDR ModeThis figure shows the soft-CDR mode datapath.


In soft-CDR mode, the synchronizer block is inactive. The DPA circuitry selects an optimal DPA clock phase to sample the data. This clock is used for bit slip operation and deserialization. The DPA block also forwards the selected DPA clock, divided by the deserialization factor called rx_divfwdclk, to the FPGA fabric, along with the deserialized data. This clock signal is put on the periphery clock (PCLK) network.

If you use the soft-CDR mode, do not assert the rx_dpa_reset port after the DPA has trained. The DPA continuously chooses new phase taps from the PLL to track parts per million (PPM) differences between the reference clock and incoming data.

You can use every LVDS channel in soft-CDR mode and drive the FPGA fabric using the PCLK network in the Intel® Stratix® 10 device family. In soft-CDR mode, the rx_dpa_locked signal is not valid because the DPA continuously changes its phase to track PPM differences between the upstream transmitter and the local receiver input reference clocks. However, you can use the rx_dpa_locked signal to determine the initial DPA locking conditions that indicate the DPA has selected the optimal phase tap to capture the data. The rx_dpa_locked signal is expected to deassert when operating in soft-CDR mode. The parallel clock, rx_coreclock, generated by the I/O PLLs, is also forwarded to the FPGA fabric.

Note: In soft-CDR mode, you must place all receiver channels of an LVDS instance in one I/O bank. Because each I/O bank has a maximum of 12 PCLK resources, each LVDS instance can support a maximum of 12 soft-CDR channels.

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