Visible to Intel only — GUID: sam1412833558707
Ixiasoft
Visible to Intel only — GUID: sam1412833558707
Ixiasoft
4.1.4.3. Bitslip
The data slips one bit for every pulse of the rx_bitslip_ctrl signal. Because it takes at least two core clock cycles to clear the undefined data, wait at least four core clock cycles before checking if the data is aligned.
After enough bitslip signals are sent to rollover the bitslip counter, the rx_bitslip_max status signal is asserted after four core clock cycles to indicate that the bitslip counter rollover point has reached its maximum counter value.
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