Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 11/30/2022
Document Table of Contents

4.3.3. Timing Analysis for the External PLL Mode

If you enable the Use external PLL parameter in the PLL Settings tab, the IP generation does not create clock settings for the PLL input and output. You must ensure the PLL clock settings are correct.

The Intel® Quartus® Prime software derives some of the SERDES constraints from the PLL clocks. Therefore, the Intel® Quartus® Prime software must generate the external PLL clock settings before the LVDS SERDES IP clock settings. In the .qsf of your project, ensure that the line for the .ip file of the IOPLL IP appears before the line for the .ip file of the LVDS SERDES IP.

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