Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 11/30/2022
Document Table of Contents

3.1.3. Guideline: LVDS Reference Clock Source

The LVDS SERDES IP core accepts two reference clock input sources. Whichever reference clock source you select, you must ensure timing closure.
Table 8.  LVDS Reference Clock Source
Reference Clock Input Source Description Reference Clock Promotion
Dedicated reference clock input within the same I/O bank. This reference clock input source is the best choice to avoid performance and timing closure issues. Do not manually promote the reference clock.
Reference clock input from other I/O banks. This source must come from another I/O bank and not from other sources such as the hard processor system (HPS), IOPLL IP, or other IPs. You must manually promote the reference clock.

To manually promote the reference clock, include this statement in your Intel® Quartus® Prime settings file (.qsf):

set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to <name of top-level reference clock input port>