Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 3/28/2022
Public
Document Table of Contents

2.5.1.4. Deserializer

You can statically set the deserialization factor to x3, x4, x5, x6, x7, x8, x9, or x10 by using the Intel® Quartus® Prime software.

The IOE contains two data input registers that can operate in DDR or SDR mode. You can bypass the deserializer to support DDR (x2) and SDR (x1) operations. The deserializer bypass is supported through the GPIO IP core.

Figure 12. Deserializer BypassThis figure shows the deserializer bypass path.


  • If you bypass the deserializer in SDR mode:
    • The IOE data width is 1 bit.
    • Registered input path requires a clock.
    • Data is passed directly through the IOE.
  • If you bypass the deserializer in DDR mode:
    • The IOE data width is 2 bits.
    • The GPIO IP core requires a clock.
    • rx_inclock clocks the IOE register. The clock must be synchronous to rx_in.
    • You must control the data-to-clock skew.

You cannot use the DPA and data realignment circuit when you bypass the deserializer.

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