Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 3/28/2022
Public
Document Table of Contents

3.1.6.1. PLLs Driving Differential Transmitter Channels

For differential transmitters, the PLL can drive the differential transmitter channels in its own I/O bank and adjacent I/O banks. However, the PLL cannot drive the channels in a non-adjacent I/O bank.
Figure 17. PLLs Driving Differential Transmitter Channels


Figure 18. Sharing Reference Clock Source to Differential Transmitter Channels Across I/O Banks


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