Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 11/30/2022
Document Table of Contents

3.1.1. Clocking Differential Transmitters

The I/O PLL generates the load enable (load_enable) signal and the fast_clock signal (the clock running at serial data rate) that clocks the load and shift registers. You can statically set the serialization factor to x3, x4, x5, x6, x7, x8, x9, or x10 using the Intel® Quartus® Prime software. The load enable signal is derived from the serialization factor setting.

You can configure any Intel® Stratix® 10 transmitter data channel to generate a source-synchronous transmitter clock output. This flexibility allows the placement of the output clock near the data outputs to simplify board layout and reduce clock-to-data skew.

Different applications often require specific clock-to-data alignments or specific data-rate-to-clock-rate factors. You can specify these settings statically in the Intel® Quartus® Prime parameter editor:

  • The transmitter can output a clock signal at the same rate as the data with a maximum output clock frequency that each speed grade of the device supports.
  • You can divide the output clock by a factor of 1, 2, 4, 6, 8, or 10, depending on the serialization factor.
  • You can set the phase of the clock in relation to the data at 0° or 180° (edge- or center-aligned). The I/O PLLs provide additional support for other phase shifts in 45° increments.
  • If the tx_outclock has a phase shift that is not a multiple of 180°, you can only place each LVDS SERDES Intel® FPGA IP transmitter interface within a single I/O bank.
Figure 16. Transmitter in Clock Output ModeThis figure shows the transmitter in clock output mode. In clock output mode, you can use an LVDS channel as a clock output channel.