Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 3/28/2022
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3.1.7.2. IOPLL Parameter Values for External PLL Mode

These examples show the clocking requirements to generate output clocks for LVDS SERDES IP using the IOPLL IP. The examples set the phase shift with the assumption that the clock and data are edge-aligned at the pins of the device.
Note: For other clock and data phase relationships, Intel recommends that you first instantiate your LVDS SERDES IP interface without using the external PLL mode option. Compile the IPs in the Intel® Quartus® Prime software and take note of the frequency, phase shift, and duty cycle settings for each clock output. Enter these settings in the IOPLL IP parameter editor and then connect the appropriate output to the LVDS SERDES IPs.
Table 11.  Example: Generating Output Clocks Using an IOPLL IP (Receiver in Non-DPA Mode) This table lists the parameter values that you can set in the IOPLL IP parameter editor to generate three output clocks using an IOPLL IP if you are using the non-DPA receiver.
Parameter

outclk0

(Connects as lvds_clk[0] to the ext_fclk port of LVDS SERDES IP transmitter or receiver)

outclk1

(Connects as loaden[0] to the ext_loaden port of LVDS SERDES IP transmitter or receiver)

outclk4 2

(Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_coreclock port of LVDS SERDES IP)

Frequency

data rate

data rate/serialization factor

data rate/serialization factor

Phase shift

180°

[(deserialization factor – 1)/deserialization factor] × 360°

180/serialization factor

(outclk0 phase shift divided by the serialization factor)

Duty cycle

50%

100/serialization factor

50%

The calculations for phase shift, using the RSKM equation, assume that the input clock and serial data are edge aligned. Introducing a phase shift of 180° to sampling clock (outclk0) ensures that the input data is center-aligned with respect to the outclk0, as shown in the following figure.

Figure 23. Phase Relationship for External PLL Interface Signals


Table 12.  Example: Generating Output Clocks Using an IOPLL IP core (Receiver in DPA or Soft-CDR Mode)This table lists the parameter values that you can set in the IOPLL IP parameter editor to generate four output clocks using an IOPLL IP if you are using the DPA or soft-CDR receiver.
Parameter

outclk0

(Connects as lvds_clk[0] to the ext_fclk port of LVDS SERDES IP core transmitter or receiver)

outclk1

(Connects as loaden[0] to the ext_loaden port of LVDS SERDES IP transmitter or receiver)

Not required for the soft-CDR receiver.

outclk42

(Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_coreclock port of LVDS SERDES IP)

VCO Frequency

(Connects as phout[7:0] to the ext_vcoph[7:0] port of LVDS SERDES IP)

Frequency

data rate

data rate/serialization factor

data rate/serialization factor

data rate

Phase shift

180°

[(deserialization factor – 1)/deserialization factor] × 360°

180/serialization factor

(outclk0 phase shift divided by the serialization factor)

Duty cycle

50%

100/serialization factor

50%

Table 13.   Example: Generating Output Clocks Using a Shared IOPLL IP for Transmitter Spanning Multiple Banks Shared with Receiver Channels (Receiver in DPA or Soft-CDR Mode) This table lists the parameter values that you can set in the IOPLL IP parameter editor to generate six output clocks using an IOPLL IP. Use these settings if you use transmitter channels that span multiple banks shared with receiver channels in DPA or soft-CDR mode.
Parameter

outclk0

(Connects as lvds_clk[0] to the ext_fclk port of LVDS SERDES IP receiver)

outclk1

(Connects as loaden[0] to the ext_loaden port of LVDS SERDES IP core receiver)

Not required for the soft-CDR receiver.

outclk42

(Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_coreclock port of LVDS SERDES IP)

VCO Frequency

(Connects as phout[7:0] to the ext_vcoph[7:0] port of LVDS SERDES IP)

outclk2

(Connects as lvds_clk[1] to the ext_fclk port of LVDS SERDES IP transmitter)

outclk3

(Connects as loaden[1] to the ext_loaden port of LVDS SERDES IP core transmitter)

Frequency

data rate

data rate/serialization factor

data rate/serialization factor

data rate

Phase shift

180°

[(deserialization factor – 1)/deserialization factor] × 360°

180/serialization factor

(outclk0 phase shift divided by the serialization factor)

Duty cycle

50%

100/serialization factor

50%

2 Not required if your turn on Use the CPA block for improved periphery-core timing.

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