Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 3/28/2022
Public
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3.5.2. Using an External PLL

  • To use an external PLL, in the LVDS SERDES IP parameter editor, turn on the Use external PLL option.
  • You can generate two instances of the LVDS SERDES IP—a receiver and a transmitter.
  • In each instance, you can use up to the following number of channels:
    • 71 transmitters
    • 23 DPA or non-DPA receivers
    • 12 soft-CDR receivers
  • Generate the IOPLL Intel FPGA IP and ensure that the .qsf file lists the IOPLL IP before the LVDS SERDES IP. This order is required for your design to compile with the proper clock constraints.
  • Connect the same PLL to both the transmitter and receiver instances.
Figure 31. LVDS Interface with the IOPLL IP (Non-DPA or DPA Mode)This figure shows the connections you need to make between the IOPLL IP and the LVDS SERDES IP in external PLL mode if you are using DPA.


Figure 32. LVDS Interface with the IOPLL IP (Soft-CDR Mode)This figure shows the connections you need to make between the IOPLL IP and the LVDS SERDES IP core if you are using soft-CDR mode.


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