Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 3/28/2022
Public
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1.3. Intel® Stratix® 10 GPIO Banks, SERDES, and DPA Locations

The I/O banks are located in I/O columns. Each I/O bank contains its own PLL, dynamic phase alignment (DPA), and SERDES circuitries.
Figure 1. I/O Bank Structure with I/O PLL, DPA, and SERDESThis figure shows an example of I/O banks in one Intel® Stratix® 10 device. The I/O banks availability and locations vary among Intel® Stratix® 10 devices.


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