E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021

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Document Table of Contents Ethernet 25G x 4 (FEC Off)

This use case does not include FEC; therefore, there is no need for clock sharing between the four 25G Ethernet channels. Connect o_clk_pll_div64 (402.83 MHz) to i_sl_clk_tx and i_sl_clk_rx. Due to the timing constraint, i_sl_clk_tx and i_sl_clk_rx channels can only be assigned to channel 0, channel 1, or channel 2.
Note: Due to the clock assignment dependency, if clock arrives from other than a master channel, the clock's appropriate channel impacts all other channels.
If you use any other source for i_sl_clk_tx or i_sl_clk_rx, make sure i_sl_clk_tx and i_sl_clk_rx have 0 PPM difference with the o_clk_pll_div64.
Figure 63. Ethernet 25G x 4 (FEC Off)