E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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3.10.9.3. RS-FEC Reconfiguration Interface

The RS-FEC reconfiguration interface is only available when you generate the IP core variation for 10.13, 12.16, and 24.3 Gbps CPRI line bit rates.
Table 105.  RS-FEC Reconfiguration Signals
Port Name Width Domain Description
i_rsfec_reconfig_address[n] 11 bits per channel i_reconfig_clk Specifies the RS-FEC Avalon® memory-mapped interface address in the selected channel.
i_rsfec_reconfig_read[n] 1 bit per channel i_reconfig_clk The IP core asserts RS-FEC read signal to start a read cycle in a selected channel.
i_rsfec_reconfig_write[n] 1 bit per channel i_reconfig_clk The IP core asserts RS-FEC write signal to write data on the reconfig_writedata bus in a selected channel.
i_rsfec_reconfig_writedata[n] 8 bits per channel i_reconfig_clk Specifies RS-FEC data to be written on a write cycle in a selected channel.
o_rsfec_reconfig_readdata[n] 8 bits per channel i_reconfig_clk Specifies RS-FEC data to be read by ready cycle in a selected channel.
o_rsfec_reconfig_waitrequest[n] 1 bit per channel i_reconfig_clk Represents RS-FEC Avalon® memory-mapped interface stalling signal in a selected channel. The read and write cycle is complete when this signal is low.

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