E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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2.9.3.1. PCS Only Mode

The E-Tile Hard IP for Ethernet Intel FPGA IP supports PCS only mode in 10/25G and 100G variants with optional RSFEC feature. It can support up to four PCS channels in 10/25G variant. This mode bypassed the Ethernet MAC and uses MII interface to read and write to the PMA block.

The PCS TX datapath consists of:
  • TX PCS encoder—encodes the data from the PMA interface.
  • TX PCS scrambler—enables the data to be scrambled. Channels will not lock correctly if the data is not scrambled.
  • Alignment insertion—the TX PCS interface inserts alignment markers.
  • Striper—enables logically sequential data to be segmented to increase data throughput.
The PCS RX datapath consists of:
  • Aligner—enables the alignment of incoming data.
  • RX PCS descrambler—enables the incoming scrambled data to be descrambled.
  • RX PCS decoder—decodes the incoming encoded data from the PMA interface.

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