E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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Document Table of Contents

2.12.3.9. TX MAC Source Address Higher Bytes

Offset: 0x40D

TX MAC Source Address Higher Bytes Fields

Bit Name Description Access Reset
15:0 saddrh Source Address Insertion Source Address upper bytes
Upper 2 bytes of the 6 byte source address that is inserted by the TX MAC when TX source address insertion is enabled
  • At power-on, saddrh is set to 1
  • After i_csr_rst_n is asserted, saddrh is set to the value given by module parameter txmac_saddr[47:32]
RW 0x11

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