E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021

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Document Table of Contents Auto Negotiation Config Register 4

Offset: 0xC4

Auto Negotiation Config Register 4 Fields

Bit Name Description Access Reset
31:0 user_base_page_high User Controlled AN Base page (upper bits)

[31:30] = FEC bits

[29:5] = Technology Ability bits

[4:0] = TX Nonce bits

RW 0x0