E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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Document Table of Contents

2.12.2.6. RX CDR PLL Locked

Offset: 0x321

RX CDR PLL Locked Fields

Bit Name Description Access Reset
3:0 eio_freq_lock CDR PLL locked

1: Corresponding physical lane's CDR has locked to data for a 100G link.

RO 0x0

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