E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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2.12.5.36. Lower 4 bytes of the Destination address for RX Pause Frames

Offset: 0x707

Lower 4 bytes of the Destination address for RX Pause Frames Fields

Bit Name Description Access Reset
31:0 rx_pause_daddrl Lower bytes of the RX Flow Control Destination Address
Lower 4 bytes of the 6 byte destination address that must be found in incoming SFC and PFC frames.
  • This feature requires EHIP to be in a mode with the MAC turned on
  • When this setting is changed, the RX MAC must be reset
  • At power-on, this register defaults to 32'hB8353715
  • When i_csr_rst_n is asserted, this register is set to the value given by the module parameter rx_pause_daddr[31:0]
RW 0xB8353715

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