E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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Document Table of Contents

2.12.2.18. PCS Virtual Lane 1

Offset: 0x331

PCS Virtual Lane 1 Fields

Bit Name Description Access Reset
29:25 vlane11 Virtual lane mapping

Original virtual lane position of the data mapped to the PCS lane with this index.

For example, if you read the value 5 from vlane12, it means the virtual lane data that the link partner transmitted on virtual lane 5 is being received on virtual lane 12. EHIP will reorder the data automatically

RO 0x1F
24:20 vlane10
19:15 vlane9
14:10 vlane8
9:5 vlane7
4:0 vlane6

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