E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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2.9.1.4. Pause Control and Generation Interface

The flow control interface implements PAUSE as specified by the IEEE 802.3ba 2010 High Speed Ethernet Standard, PFC as specified by the IEEE Standard 802.1Qbb.

You can configure the PAUSE logic to automatically stop local packet transmission when the link partner sends a PAUSE XOFF packet. The PAUSE logic can pass the PAUSE packets through as normal packets or drop the packets before they reach the RX client.

As for PFC frames, you can configure the PFC logic to pass the PFC packets through as normal packets or drop them before they reach the RX client. However, you don't have an option to stop traffic automatically when a PFC XOFF frame arrives.

Table 21.  Pause Control and Generation SignalsDescribes the signals that implement pause control. These signals are available only if you turn on flow control in the E-Tile Hard IP for Ethernet Intel FPGA IP parameter editor.
Note: The signal names may have slight variance depending on the variant you select.

Signal Name

Direction

Description

i_tx_pause (PAUSE)

i_tx_pfc (PFC)

Input

Level signal which directs the IP core to insert a PAUSE or PFC frame for priority traffic class [n] on the Ethernet link. If bit [n] of the TX_PAUSE_EN register has the value of 1, the IP core transmits an XOFF frame when this signal is first asserted. If you enable retransmission, the IP core continues to transmit XOFF frames periodically until the signal is de-asserted. When the signal is deasserted, the IP core inserts an XON frame.

o_rx_pause (PAUSE)

o_rx_pfc (PFC)

Output

Asserted to indicate an RX a PAUSE or PFC signal match. The IP core asserts bit [n] of this signal when it receives a pause request with an address match, to signal the TX MAC to throttle its transmissions from priority queue [n] on the Ethernet link.

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