E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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2.11.17.3.6. 10G/25G Ethernet Channel with Advanced PTP Accuracy Mode

When PTP is enabled, the external AIB clocking is inherently enabled. Do not enable External AIB clocking parameter in the Parameter Editor, it is unnecessary and redundant.

Table 67.  Use Case Configuration
Number of Ethernet Channels Data Rate Core Interface External AIB Clocking
2 25.78125 Gbps 64 bits Disabled

This use case covers a scenario when PTP is enabled and the PTP Accuracy Mode is set to Advanced Mode.

With PTP enabled, a PTP channel and its source clock called PTP clock becomes the master channel regardless of FEC configuration.

Connect o_clk_pll_div66[number of channel] to the i_sl_clk_tod[number or channels], and o_clk_rec_div66[number of channels] to the i_sl_clk_rx_tod[number of channels] of each Ethernet channel based on the following guidelines:
Table 68.  Clock Connection Guidelines for 10GE/25GE with enabled PTP and Advanced PTP Accuracy Mode
Number of Channels of 10G/25G Clock Port PTP Clock Clock Connection Guideline
Single channel

i_sl_clk_tx

i_sl_clk_rx

i_sl_clk_tx_tod

i_sl_clk_rx_tod

o_clk_pll_div64[1]

Connect o_clk_pll_div64[1] to i_sl_clk_tx and i_sl_clk_rx.

Connect o_clk_pll_div66 to i_sl_clk_tx_tod.

Connect o_clk_rec_div66 to i_sl_clk_rx_tod.

2 channels

i_sl_clk_tx[1:0]

i_sl_clk_rx[1:0]

i_sl_clk_tx_tod[1:0]

i_sl_clk_rx_tod[1:0]

o_clk_pll_div64[2]

Connect o_clk_pll_div64[2] to

i_sl_clk_tx[1:0] and i_sl_clk_rx[1:0].

Connect o_clk_pll_div66[1:0] to i_sl_clk_tx_tod[1:0].

Connect o_clk_rec_div66[1:0] to i_sl_clk_rx_tod[1:0].

3 channels

i_sl_clk_tx[2:0]

i_sl_clk_rx[2:0]

i_sl_clk_tx_tod[2:0]

i_sl_clk_rx_tod[2:0]

o_clk_pll_div64[3]

Connect o_clk_pll_div64[3] to

i_sl_clk_tx[2:0] and i_sl_clk_rx[2:0].

Connect o_clk_pll_div66[2:0] to i_sl_clk_tx_tod[2:0].

Connect o_clk_rec_div66[2:0] to i_sl_clk_rx_tod[2:0].

4 channels

i_sl_clk_tx[2:0]

i_sl_clk_rx[2:0]

i_sl_clk_tx_tod[3:0]

i_sl_clk_rx_tod[3:0]

o_clk_pll_div64[4]

Connect o_clk_pll_div64[4] to

i_sl_clk_tx[3:0] and i_sl_clk_rx[3:0].

Connect o_clk_pll_div66[3:0] to i_sl_clk_tx_tod[3:0].

Connect o_clk_rec_div66[3:0] to i_sl_clk_rx_tod[3:0].

Figure 65. Ethernet 25G with Advanced PTP Accuracy Mode

In addition, the advanced mode requires an IOPLL to provide a clock frequency of 114.285714 MHz to connect to i_clk_ptp_sample. The IOPLL must be a stable, free running clock with the reference frequency meeting the IOPLL reference clock requirement as specified in the Intel® Stratix® 10 Clocking and PLL User Guide. You can also use any existing IOPLL in the your design to generate this required clock frequency.

Table 69.  Recommended Connection Guidelines for IOPLL Signals
IOPLL Signals Description
refclk

Any system clock that meets the reference clock requirement.

The default frequency is 100 MHz. The minimum and maximum frequency value depends on the selected device.

rst Global/system reset
locked Logic reset
outclk_0 i_clk_ptp_sample

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