E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.12.5.12. Higher 2 bytes of the Destination address for Flow Control

Offset: 0x60E

Higher 2 bytes of the Destination address for Flow Control Fields

Bit Name Description Access Reset
15:0 daddrh Flow control Destination Address
Upper 2 bytes of the 6 byte destination address used for SFC and PFC frames
  • At power-on, daddrh is set to 16'h0180
  • After i_csr_rst_n is asserted, daddrh is set to the value given by module parameter tx_pause_daddr[47:32]
RW 0x180

Did you find the information on this page useful?

Characters remaining:

Feedback Message