E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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2.12.1.6. Auto Negotiation Config Register 3

Offset: 0xC3

Auto Negotiation Config Register 3 Fields

Bit Name Description Access Reset
30:28 override_an_pause AN_PAUSE Override Value

When Override AN Parameters is enabled (override_an_parameters_enable=1), this register controls the value of AN_PAUSE used in the AN Base page

[0]: Pause Ability

[1]: Asymmetric Direction

[2]: Reserved

RW 0x0
27:24 override_an_fec AN_FEC Override Value

When Override AN Parameters is enabled (override_an_parameters_enable=1), this register controls the value of AN_FEC used in the AN Base page

[24] = 10G BASE-R RS-FEC Capability

[25] = 10G BASE-R RS-FEC Request

[26] = 25G IEEE RS-FEC Request

[27] = 25G IEEE BASE-R RS-FEC Request

RW 0x0
23:16 override_an_tech AN_TECH Override Value, bits [7:0]

When Override AN Parameters is enabled (override_an_parameters_enable=1), this register controls the value of AN_TECH used in the AN Base page

[16] = Reserved

[17] = 10GBASE-KX4 (XAUI)

[18] = 10GBASE-KR

[19] = Reserved

[20] = Reserved

[21] = Reserved

[22] = 100GBASE-KP4

[23] = 100GBASE-KR4

RW 0x0
15:0 user_base_page_low User Controlled AN Base page (lower bits)

When User Controlled Base pages are turned on (an_base_pages_ctrl=1), this register provides the lower bits of the User base page that is used instead of the default page

[15] = Next page bit

[14] = ACK bit (controlled by State Machine)

[13] = Remote Fault bit [12:10]: Pause bits

[9:5] = Echoed Nonce (set by SM)

[4:0] = Selector

Note: Bit 49 (the PRBS bit of the AN BASE page) is generated by the SM.
RW 0x0

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