E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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Document Table of Contents

2.12.2.3. Loopback Mode

Offset: 0x30D

Loopback Mode

Registers to control the muxes that determine the loopback mode.
Bit Name Description Access Reset
23:21 rxpldmux_sel Select the input to the RX PLD Interface
  • 7: TX PLD Interface
  • 1: RX PCS
  • 0: RX MAC
RW 0x0
20:18 rxmacmux_sel Select the input to the RX MAC
  • 2: TX MAC
  • 0: RX PCS
RW 0x0
17:15 rxpcsmux_sel Select the input to the RX PCS
  • 3: TX PCS
  • 0: RX PMA Interface

The RX datapath must be reset after changing this setting.

RW 0x0
5:3 txpcsmux_sel Select input to TX PCS
  • 2: RX PCS
  • 1: TX PLD Interface
  • 0: TX MAC
RW 0x0

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