2. About the E-Tile Hard IP for Ethernet Intel FPGA IP Core
Intel® Stratix® 10 and Intel® Agilex™ E-tile FPGA production devices include a configurable, hardened protocol stack for Ethernet that is compatible with the IEEE 802.3 High Speed Ethernet Standard and the 25G/50G Ethernet Specification, Draft 1.6 from the 25 Gigabit Ethernet Consortium.
|Supported Device Family||IP Catalog|
|Intel® Stratix® 10||E-Tile Hard IP for Ethernet Intel® FPGA IP|
|Intel® Agilex™||E-Tile Ethernet IP for Intel® Agilex™ FPGA|
The E-Tile Hard IP for Ethernet Intel FPGA IP provides access to this hard IP at Ethernet data rates of 10 Gbps, 25 Gbps, and 100 Gbps. The IP core is included in the Intel® FPGA IP Library and is available from the Intel® Quartus® Prime Pro Edition IP Catalog.
- Single 10GE/25GE channel
- 1 to 4 10GE/25GE channels with optional Reed-Solomon Forward Error Correction (RS-FEC)
- 100GE channel with optional RS-FEC
- 100GE or 1 to 4 10GE/25GE channels with optional RS-FEC, and optional 1588 Precision Time Protocol (PTP)
- Custom PCS with optional RS-FEC
The 100GE or 1 to 4 10GE/25GE channels with optional RS-FEC, and optional 1588 Precision Time Protocol (PTP) variant contains a 100G Ethernet channel, and up to 4 single-lane channels that can run at 10G or 25G. However, the single-lane channels and the 100GE channel cannot run at the same time.
For any variant except the custom PCS with RS-FEC variant, you can choose a Media Access Control (MAC) + Physical Coding Sublayer(PCS) variation, a PCS-only variation, a custom PCS variation, a Flexible Ethernet (FlexE) variation, or an Optical Transport Network (OTN) variation.
|IP Core Variation||Client Interface Type|
|MAC+PCS||Avalon® Streaming ( Avalon® -ST) 1|
|PCS_Only||Media Independent Interface (MII)|
E-Tile Hard IP for Ethernet Intel FPGA IP core supports a variety of protocol implementations.
|Ethernet Channel||Protocol||Number of Lanes and Line Rate|
|100GE||100GBASE-KR4||4x25.78125 Gbps Non-Return-to-Zero (NRZ) lanes for Copper Backplane|
|100GBASE-CR4||4x25.78125 Gbps NRZ lanes for Direct Attach Copper Cable|
|CAUI-4||4x25.78125 Gbps NRZ lanes for Low Loss Links: Chip-to-Chip or Chip-to-Module|
|100GBASE-KR2||2x53.125 Gbps PAM4 lanes for Copper Backplane|
|100GBASE-CR2||2x53.125 Gbps PAM4 lanes for Direct Attach Copper Cable|
|CAUI-2||2x53.125 Gbps PAM4 lanes for Low Loss Links: Chip-to-Chip, Chip-to-Module|
|25GE||25GBASE-KR||1x25.78125 Gbps NRZ lane for Copper Backplane|
|25GBASE-CR||1x25.78125 Gbps NRZ lane for Direct Attach Copper Cable|
|25GBASE-R AUI||1x25.78125 Gbps NRZ lane for Low Loss Connections to External PHY Modules|
|25GBASE-R Consortium Link||1x25.78125 Gbps NRZ lane based on the 25G/50G Consortium Specification|
|10GE||10GBASE-KR||1x10.3125 Gbps NRZ lane for Copper Backplane|
|10GBASE-CR||1x10.3125 Gbps NRZ lane for Direct Attach Copper Cable|
|XAUI||1x10.3125 Gbps NRZ lane for Low Loss Connections to External PHY Modules|
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