E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.2.1. Features

The Ethernet Toolkit offers the following features when used with hardware design that has standalone Ethernet IP as well as with an Intel® Quartus® Prime generated Ethernet IP design example:
  • Verifies the status of the Ethernet link.
  • Reads and writes to status and configuration registers of the IP.
  • Displays the values of TX/RX status and statistics registers.
  • Ability to assert and deassert IP resets.
  • Verifies the IPs error correction capability.

The Ethernet Toolkit also offers some additional features when used with an Intel® Quartus® Prime generated Ethernet IP design example:
  • Provides access to the example design packet generator.
  • Execute testing procedures to verify the functionality of Ethernet IPs.
  • Enable and disable MAC loopback.
  • Set source and destination MAC addresses.

Did you find the information on this page useful?

Characters remaining:

Feedback Message