E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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2.9.2.4. PTP Receive Functionality

If you turn on Enable IEEE 1588 PTP in the E-Tile Hard IP for Ethernet Intel FPGA IP parameter editor, the IP core provides a 96-bit (V2 format) with every packet on the RX client interface, whether it is a 1588 PTP packet or not. The value on the timestamp bus o_ptp_rx_its is valid in the same clock cycle as the RX SOP signal. The value on the timestamp bus is not the current timestamp; instead, it is the timestamp from the time when the IP core received the packet on the Ethernet link. The IP core captures the time-of-day from the TOD module on i_ptp_tod at the time it receives the packet on the Ethernet link, and sends that timestamp to the client on the RX SOP cycle on the timestamp bus o_ptp_rx_its. User software/hardware logic can use this timestamp or ignore it based on whether it is a 1588 PTP packet or not.

The RX PTP operation assumes the o_sl_rx_ptp_ready signal was asserted and is held high.

Figure 28. PTP Receive Block Diagram
Figure 29. Example Waveform PTP Timestamp on RX PTP Interface

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