E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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2.9.2.1. Implementing a 1588 System That Includes a E-Tile Hard IP for Ethernet Intel FPGA IP

The 1588 specification in IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control Systems Standard describes various systems you can implement in hardware and software to synchronize clocks in a distributed system by communicating time offset and frequency correction information between master and slave clocks in arbitrarily complex systems. A 1588 system that includes the E-Tile Hard IP for Ethernet Intel® FPGA IP with 1588 PTP functionality uses the incoming and outgoing timestamp information from the IP core and the other modules in the system to synchronize clocks across the system.

The E-Tile Hard IP for Ethernet Intel® FPGA IP with 1588 PTP functionality provides the timestamp manipulation and basic update capabilities required to integrate your IP core in a 1588 system. You can specify that packets are PTP packets, and how the IP core should update incoming timestamps from the client interface before transmitting them on the Ethernet link. The IP core does not implement the event messaging layers of the protocol, but rather provides the basic hardware capabilities that support a system in implementing the full 1588 protocol.

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