E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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Document Table of Contents

2.12.1.10. Auto Negotiation Status Register 1

Offset = 0xC7

Auto Negotiation Status Register 1 Fields

Bit Name Description Access Reset
15:0 lp_base_page_low Link Partner Base Page (lower bits)

[15] = Link partner next page bit

[14] = Link partner ACK

[13] = Link partner RF bit

[12:10] = Link partner PAUSE bits

[9:5] = Link partner Echoed Nonce bits

[4:0] = Link partner Selector bits

RO 0x0

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