E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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2.11.17.3.1. Single 25G Ethernet Channel (with FEC)

Table 62.  Use Case Configuration
Data Rate Core Interface
25.78125 Gbps 64 bits

Connect o_clk_pll_div64 (402.83MHz) to the i_sl_clk_tx and i_sl_clk_rx. If you use any other source for i_sl_clk_tx or i_sl_clk_rx, make sure that i_sl_clk_tx and i_sl_clk_rx have 0 PPM difference with respect to o_clk_pll_div64.

Figure 58. Ethernet 25G x 1RX FEC is also clocked by the TX PMA generated clock.

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