E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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2.9.2.6. PTP Timestamp and TOD Formats

The E-Tile Hard IP for Ethernet Intel® FPGA IP supports a 96-bit timestamp (V2 format) or a 64-bit timestamp (correction-field format) in PTP packets.

The IP core completes all internal processing in the V2 format. However, if you specify V1 format for a particular PTP packet in one-step insertion mode, the IP core inserts the appropriate V1-format timestamp in the outgoing packet on the Ethernet link.

V2 Format

The IP core maintains the time-of-day (TOD) in V2 format according to the IEEE specification::

  • Bits [95:48]: Seconds (48 bits).
  • Bits [47:16]: Nanoseconds (32 bits). This field overflows at 1 billion.
  • Bits [15:0]: Fractions of nanosecond (16 bits). This field is a true fraction; it overflows at 0xFFFF.

V1 Format

V1 timestamp format is specified in the IEEE specification:

  • Bits [63:32]: Seconds (32 bits).
  • Bits [31:0]: Nanoseconds (32 bits). This field overflows at 1 billion.
Note: PTP packet with V1 timestamp format and Extended bytes is not supported for channel that uses a mixture of V1 and V2 timestamp formats.

Correction Field Format

The Correction Field format is distinct from the V1 format. It is intended for use in transparent clock systems, in which each node adds its own residence time to a running total latency through the system. This format matches the format of the correction field in the packet, as used in transparent clock mode.

  • Bits [63:16]: Nanoseconds (48 bits).
  • Bits [15:0]: Fractions of nanosecond (16 bits). This field is a true fraction; it overflows at 0xFFFF.

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