E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.9.2.9. 100G PTP TX User Flow

In this section, the acronym PL and VL stands for Physical Lane and Virtual Lane respectively.
  1. After power up or reset, wait until TX raw offset data are ready.
    The status could be monitored via:
    • Polling via CSR:
      csr_read (mlptp_status[0]) = 1’b1
  2. Read TX raw offset data from IP:
    tx_const_delay = csr_read (mlptp_tx_const_delay[30:0])
    tx_const_delay_sign = csr_read (mlptp_tx_const_delay[31])
    
    for (pl = 0; pl < PL; pl++) {
    	tx_apulse_offset[pl] = csr_read (mlptp_tx_l<3-0>_offset[30:0])
    	tx_apulse_offset_sign[pl] = csr_read (mlptp_tx_l<3-0>_offset[31])
    	tx_apulse_wdelay[pl] = csr_read (mlptp_tx_l<3-0>_wire_dly[19:0])
    	tx_apulse_time[pl] = csr_read (mlptp_tx_l<3-0>_time[19:0])
    }
    
  3. Determine TX reference lane:
    1. Detect if asynchronous pulse time rollover, and adjust accordingly:
      Expectation: Skew between async pulses < 256ns
      
      tx_ap_time_rollover = ((max(tx_apulse_time[PL-1:0]) – min(tx_apulse_time[PL-1:0])) > 256ns) ? 1 : 0
      
      tx_ap_time_seconds_rollover = (tx_ap_time_rollover && (29’h10000000 – max(tx_apulse_time[PL-1:0])) > 256ns) ? 1 : 0
      
      for (pl = 0; pl < PL; pl++) {
      tx_apulse_time_adj[pl] = tx_ap_time_seconds_rollover && (tx_apulse_time[pl] < 256ns) ? tx_apulse_time[pl] + {13’h0A00, 16’h0000} : tx_ap_time_rollover && (tx_apulse_time[pl] < 256ns) ? tx_apulse_time[pl] + {13’h1000, 16’h0000} : tx_apulse_time[pl]
      }
      
    2. Calculate the actual time of TX Alignment Marker at TX PMA parallel data interface:
      for (pl = 0; pl < PL; pl++) {
      tx_am_actual_time[pl] = (tx_apulse_time_adj[pl]) + (tx_apulse_offset_sign[pl] ? –tx_apulse_offset[pl] : tx_apulse_offset[pl]) – (tx_apulse_wdelay[pl])
      }
      
    3. Determine TX reference lane:
      tx_ref_pl = pl
      
      where tx_am_actual_time[pl] is max(tx_am_actual_time[PL-1:0])
  4. Calculate TX offsets:
    1. Calculate TX TAM adjust:
      tx_tam_adjust = (tx_const_delay_sign ? –tx_const_delay : tx_const_delay) + (tx_apulse_offset_sign[tx_ref_pl] ? –tx_apulse_offset[tx_ref_pl] : tx_apulse_offset[tx_ref_pl]) – (tx_apulse_wdelay[tx_ref_pl])
      
    2. Calculate TX extra latency:
      Convert unit of TX PMA delay from UI to nanoseconds:
      tx_pma_delay_ns = tx_pma_delay_ui * UI
      Total up all extra latency together:
      tx_extra_latency = tx_pma_delay_ns + tx_external_phy_delay + tx_tam_adjust
  5. Write the determined TX reference lane into IP:
    csr_write (mlptp_tx_ref_lane, tx_ref_pl)
  6. Write the calculated TX offsets to IP:
    1. Write TX extra latency:
      csr_write (tx_ptp_extra_latency, tx_extra_latency)
  7. UI value measurement. Follow the steps mentioned in section 100G UI Adjustment.
    Note: As UI measurement is a long process in simulation. Therefore, for simulation, Intel recommends to skip this step and program 0 ppm value.
  8. Notify soft PTP that user flow configuration is completed:
    csr_write (mlptp_tx_user_cfg, 1’b1)
  9. Wait until TX PTP is ready.
    The status could be monitored via:
    • Output port:
      o_tx_ptp_ready = 1’b1
      or
    • Polling via CSR:
      csr_read (mlptp_status[2]) = 1’b1
  10. TX PTP is up and running.
    1. Adjust TX UI value. You must perform TX UI adjustment of IP from time to time to prevent time counter drift from golden time-of-day in the system. Follow the steps mentioned in section 100G UI Adjustment.
      Note: UI measurement is a long process in simulation. Therefore, for simulation, Intel recommends to skip this step and program 0 ppm value.

Did you find the information on this page useful?

Characters remaining:

Feedback Message