E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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3.7.4.5. Restrictions

The master channel provides the clock for slave channels to use for clocking their TX and RX data paths. Any interruption to that clock from master channel impacts the already running slave channels. This creates a dependency between the master and the slave channels.

If master channel and slave channels are running at high speed CPRI data rates, and you switch the master channel high speed CPRI data rate to any of the low speed CPRI data rates, the slave channels go down since the clock from master channel is interrupted, as shown in Figure: Master Channel Switch from high speed CPRI data rates with or without RS-FEC to low speed CPRI data rates below.
Note: The high speed CPRI data rates are 24.3, 12.1, and 10.1 Gbps with and without RS-FEC. The low speed CPRI data rates are 2.4, 3.0, 4.9, 6.1, and 9.8 Gbps.
Figure 82. Master Channel Switch from high speed CPRI data rates with or without RS-FEC to low speed CPRI data ratesIn the figure below, three high speed CPRI data rates slave channels are down.
In order to not impact slave channels which are already running at high speed CPRI data rates as shown in the above case, the master channel's rate reconfiguration should be within the data rates listed as high speed CPRI data rates. In addition to that, if master channel runs at any of the high speed CPRI data rates, the slave channels have the ability to switch to any CPRI data rates as shown in Figure: Slave Channels Free to switch to any CPRI line rates.
Figure 83. Master Channel Switch within high speed CPRI data ratesIt does not impact slave channels running at high speed CPRI data rates.
Figure 84. Slave Channels Free to switch to any CPRI line rates

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