E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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Document Table of Contents

2.12.5.4. TX Pause Request

Offset: 0x606

TX Pause Request Fields

Bit Name Description Access Reset
8:0 req_pause Request TX PAUSE or TX PFC.

Bits [7:0]: For PFC

Bit [8]: For PAUSE

Set to request the transmission of TX Pause frames

Works the same way as the corresponding tx_pause port or tx_pfc port

RW 0x0

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