E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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2.12.5.11. Lower 4 bytes of the Destination address for Flow Control

Offset: 0x60D

Lower 4 bytes of the Destination address for Flow Control Fields

Bit Name Description Access Reset
31:0 daddrl Flow control Destination Address
Lower 4 bytes of the 6 byte destination address used for SFC and PFC frames
  • At power-on, daddrl is set to 32'hC2000001
  • After i_csr_rst_n is asserted, daddrl is set to the value given by module parameter tx_pause_daddr[31:0]
RW 0xC2000001

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