E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.12.5.34. Enable RX Pause Frame Processing

Offset: 0x705

Enable RX Pause Frame Processing Fields

Bit Name Description Access Reset
7:0 en_rx_pause Enable Rx Pause
1:Enable PFC port for selected queue
  • After power-on, this reset is set to 0
  • After i_csr_rst_n, this register is set to a value given by the module parameter flow_control
RW 0x1

Did you find the information on this page useful?

Characters remaining:

Feedback Message