E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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2.11.14.1. Ethernet Reconfiguration Interfaces

You access Ethernet control and status registers of the E-Tile Hard IP for Ethernet Intel FPGA IP during normal operation using an Avalon® memory-mapped interface. The interface responds regardless of the link status. It also responds when the IP core is in a reset state driven by any reset signal or soft reset other than the i_csr_rst_n signal.

Asserting the i_csr_rst_n signal resets all Ethernet control and status registers, including the statistics counters; while this reset is in process, reads or writes to addresses in the Ethernet Hard IP will be delayed.

Table 52.  Ethernet Reconfiguration InterfaceThe signals in this interface are clocked by the i_reconfig_clk clock and reset by the i_reconfig_reset signal. This clock and reset are used for all the reconfiguration interfaces in the IP core. However, the two interfaces access disjoint sets of registers. The signal names are standard Avalon® streaming interface signals with slight differences to indicate the variations. For example:
  • For variants with single 10GE/25GE channel: i_sl_eth_reconfig_addr
  • For variants with more than 1 channel: i_sl_eth_reconfig_addr[n-1:0]
  • For variants with single 100GE channel: i_eth_reconfig_addr
Port Name Width Description

i_sl_eth_reconfig_addr

i_sl_eth_reconfig_addr[n-1:0]

i_eth_reconfig_addr

21 (100GE)

19 (10GE/25GE)

Address bus for Ethernet control and status registers in the respective channel.

i_sl_eth_reconfig_write

i_sl_eth_reconfig_write[n-1:0]

i_eth_reconfig_write

1

Write request signal for Ethernet control and status registers in the respective channel.

i_sl_eth_reconfig_read

i_sl_eth_reconfig_read[n-1:0]

i_eth_reconfig_read

1

Read request signal for Ethernet control and status registers in the respective channel.

i_sl_eth_reconfig_writedata

i_sl_eth_reconfig_writedata[n-1:0]

i_eth_reconfig_writedata

32

Write data for Ethernet control and status registers in the respective channel.

i_sl_eth_reconfig_readdata

i_sl_eth_reconfig_readdata[n-1:0]

i_eth_reconfig_readdata

32

Read data from reads to Ethernet control and status registers in the respective channel.

o_sl_eth_reconfig_readdata_valid

o_sl_eth_reconfig_readdata_valid[n-1:0]

o_eth_reconfig_readdata_valid

1

Read data from Ethernet control and status registers is valid in the respective channel.

i_sl_eth_reconfig_waitrequest

i_sl_eth_reconfig_waitrequest[n-1:0]

i_eth_reconfig_waitrequest

1

Avalon® memory-mapped interface stalling signal for operations on Ethernet control and status registers in the respective channel.

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