E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021

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Document Table of Contents Transceiver Reconfiguration Interfaces

You access the control and status registers of the Intel® Stratix® 10 E-tile transceivers during normal operation using an Avalon® memory-mapped interface. The interface responds regardless of the link status.

Asserting the i_csr_rst_n signal resets all Ethernet control and status registers, including the statistics counters; while this reset is in process, the Ethernet reconfiguration interface does not respond.

Table 53.  Transceiver Reconfiguration Interface Ports to Native PHY Reconfiguration InterfacesThe signals in this interface are clocked by the i_reconfig_clk clock and reset by the i_reconfig_reset signal. All interface signals are clocked by the RX clock. The signal names are standard Avalon® memory-mapped interface signals with slight differences for different variations. For example:
  • For single 10GE/25GE channel variant: i_xcvr_reconfig_address
  • For 1–4 10GE/25GE channels variant: i_xcvr_reconfig_address[n-1:0]
  • For single 100GE channel variant:i_xcvr_reconfig_address[19*w-1:0]; each lane = 19 bit, w = 4
  • For single 100GE or 1–4 10GE/25GE channels variant: i_xcvr_reconfig_address[ch-1:0]; ch = number of transceivers
Port Name Width Description



Address bus for transceiver control and status registers.



Transceiver write signal.

When asserted, writes data on the reconfiguration write data bus.



Transceiver read signal.

When asserted, starts a read cycle.


8 bits each lane

Transceiver write data bus.

When asserted, presents transceiver data written on a write cycle.


8 bits each lane

Transceiver read data bus.

When asserted, presents transceiver data read on a read cycle.


1 Indicates the Avalon® memory-mapped interface interface is busy. The read or write cycle is only complete when this signal goes low.