E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.9.1.5. Pause Control Frame Filtering

The E-Tile Hard IP for Ethernet Intel FPGA IP supports options to enable or disable the following features for incoming pause control frames. These options are available as long as you do not set the Stop TX traffic when link partner sends pause parameter to Disable Flow Control.

For filtering, the PAUSE and PFC packets are only processed if their destination address matches the address given by the rx_pause_daddr parameter.

  • If you turn on Forward RX Pause Requests in the parameter editor, the RX PAUSE and PFC frames are always passed along the RX client, even if they are processed.
  • If you turn off Forward RX Pause Requests in the parameter editor, the RX PAUSE and PFC packets are processed internally, and not presented to the RX client as valid packets.

A PAUSE or PFC packet must have a destination address that matches the rx_pause_daddr parameter, a Length/Type field that is set to 0x8808, and the first 2 bytes of the packet set to 0x0001 or 0x0101.

To actually trigger PAUSE or PFC, you must also ensure that the packets are of the correct length and have no FCS error. Because these conditions are not known until the whole packet has arrived, if you turn off Forward RX Pause Requests , you may have packets that are filtered because they look like PAUSE or PFC packets, but not processed because they are of the wrong size or have an error.

Did you find the information on this page useful?

Characters remaining:

Feedback Message