E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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Document Table of Contents

2.12.1.2. ANLT Sequencer Status

Offset: 0xB1

ANLT Sequencer Status Fields

Bit Name Description Access Reset
31 kr_paused Indicates ANLT Function is paused due to kr_pause bit

1: ANLT Function Paused

0: Normal ANLT Function

   
18 rsfec_ability Indicates local RS-FEC support

1: RS-FEC supported

0: RS-FEC not supported

Defaults to 1 if parameter ENABLE_RSFEC is set to 1

RO 0x0
15:8 seq_reconfig_mode Sequencer mode for PCS reconfiguration

[8] = AN mode

[9] = LT mode (Clause 93)

[10] = 10G data mode

[11] = 25G data mode

[12] = Reserved

[13] = 100G-R4 data mode

[14] = Reserved

[15] = 100G-P2 data mode

All other settings reserved.

  • The sequencer modifies the datapath as required to move through the stages of ANLT
  • This status register lets you know which step is in progress, and how the datapath is configured
RO 0x0
2 seq_lt_timeout Sequencer Link Training Timeout

1: Sequencer had LT Timeout

0: No timeout occurred

This status bit is sticky, and stays high until the next time LT restarts.
RO 0x0
1 seq_an_timeout Sequencer AutoNegotiation Timeout

1: Sequencer had AN Timeout

0: No timeout occurred

This status bit is sticky, and stays high until the next time AN restarts.
RO 0x0
0 seq_link_ready Sequencer Link Ready

1: Link is ready for data mode

0: Link not ready

RO 0x0

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