E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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2.9.1.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC)

If you do not select Disable Flow Control in the Stop TX traffic when link partner sends pause parameter, the E-Tile Hard IP for Ethernet Intel FPGA IP provides flow control to reduce congestion at the local or remote link partner. When either link partner experiences congestion, the respective TX MAC can be instructed to send PAUSE or PFC frames to regulate the flow of data from the other side of the link.
  • PAUSE frames instruct the remote transmitter to stop sending data for the duration that the congested receiver specified in an incoming XOFF frame.
  • PFC frames instruct the receiver to halt the flow of packets assigned to a specific Priority Queue for a specified duration.

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