E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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2.9.2.11. 100G RX Virtual Lane Offset Calculation for No FEC Variants

  1. Lock the RX PCS. The RX PCS must be fully aligned before extracting VL Offfset data. Wait for o_rx_pcs_fully_aligned to be asserted.
  2. Read the VL data for each of the Local Virtual Lanes (VL):

    Perform the read operation via CSR interface. This returns VL data field (offsets: 0xC40 - 0xC67) data for all 20 virtual lanes.

    For example, if you read VL data for Local lane 0, you get GBSTATE[0], BA_PHASE[0], BA_POS[0], AM_COUNT[0], and REMOTE_VL[0]. LOCAL_VL will be set to 0, and LOCAL_PL will be set to 0.

  3. Set the Physical Lanes for each Remote Virtual Lane:
    Step through the data provided by each Local Virtual lane:
    • Each lane provides a REMOTE_VL and a LOCAL_PL value.

    For each of the 20 possible Remote virtual lanes, set PL[REMOTE_VL] = LOCAL_PL.

    For example, if you read Local Virtual lane 12, and get back REMOTE_VL = 5, LOCAL_PL = 2, that means the data for Virtual lane 5 from the link partner is coming in on our Physical lane 2. You store that as PL[5] = 2.

  4. Calculate the Virtual Lane Offsets for each of the Remote Virtual Lanes in bits:
    Step through the data provided by each Local Virtual lane
    Note: % is the modulo operator.
    
    Let sublane = LOCAL_VL % 5 
    	For example, if you are processing data from Local VL12, sublane is 2
    	
    Let bit_offset = ((BA_POS-21)*5-BA_PHASE*22+sublane)%66
    	For example, suppose you get BA_POS=4, BA_PHASE=0 on sublane 2
    	bit_offset = ((4-21)*5-0*22+2)%66 = (-85+2)%66 = 49
    	
    	Bit offset indicates the number of bits away from bit 0 of an incoming 
    	PL 66b block the alignment logic must shift data to align it
    	
    Let gb_shift = (GBSTATE-4 +BA_PHASE*3)%5 
    	For example, suppose you get BA_PHASE = 0, and GBSTATE = 3
    	gb_shift = (2 – 4 + 0*3)%5 = (-1)%5 = 4
    	
    Let am_shift = (AM_COUNT > (am_interval+1)/2) ? (AM_COUNT-(am_interval+1)): AM_COUNT
    	For example, suppose you get AM_COUNT=63, and am_interval is set to 63
    	63>(63+1)/2, so am_shift = (63 – (63+1)) = -1
    	Note that it is ok for am_shift to be negative
    	
    Let am_offset = am_shift * 5 + gb_shift
    	In this example, am_shift = -1, and gb_shift = 4, 
    	therefore am_offset = -1 * 5 +4 = -1
    	
    Set proc_offset as follows:
    	If(BA_PHASE == 0) {
    	   if(BA_POS ==21) { proc_offset = 4;}
    	   else if(BA_POS > 7) { proc_offset = 5;}
    	   else if(sublane ==4 && BA_POS == 6){proc_offset = 5;}
    	   else{proc_offset = 6;}
    	}
    	else if(BA_PHASE == 1){
    	   if(BA_POS > 12) { proc_offset = 5;}
    	   else if(sublane > 0 && BA_POS == 12){proc_offset = 5;}
    	   else{proc_offset = 6;}
    	}
    	else{
    	   if(BA_POS > 17) { proc_offset = 5;}
    	   else if(sublane >2 && BA_POS == 16){proc_offset = 5;}
    	   else if(BA_POS >3){proc_offset = 6;}
    	   else if(sublane >1) && BA_POS==3){proc offset =6;}
    	   else{proc_offset = 7;}
    	}
    For example:
    	if sublane == 2, BA_PHASE==0, and BA_POS==4, proc_offset = 6
    	Set vl_offset_bits[REMOTE_VL] = (bit_offset – (am_offset + proc_offset)*66)
    
    For example:
    	if REMOTE_VL=5, bit_offset = 49, am_offset = -1, and proc_offset = 6
    	Set vl_offset_bits[5]  = (49 – (-1+6)*66) = -281 bits
    In this case, the reference block actually arrived 281 UI later than the Alignment marker. To compute the time that the alignment marker arrived, take the time of the reference block arrival, and subtract 281.
    
  5. Convert the vl_offset_bits to VL_OFFSET (in ns):
    For each REMOTE_VL, VL_OFFSET[REMOTE_VL] = vl_offset_bits_shifted[REMOTE_VL] * RX_UI

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