E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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Document Table of Contents

2.12.2.25. Status for Dynamic Deskew Buffer

Offset: 0x354

Status for Dynamic Deskew Buffer Fields

Bit Name Description Access Reset
16 err_skew Dynamic Deskew Buffer overflow
1: At least one lane of the Dynamic Deskew Buffer overflowed sometime in the past since the last time it was reset
  • Once asserted, the value will hold until the you clears it using the i_clear_internal_err port, or by resetting the RX datapath
  • The dynamic deskew buffer should be cleared by deasserting i_signal_ok, or by resetting the RX datapath
  • When a dynamic deskew buffer overflows, RX data is lost, which can cause packets to be lost, and frame errors
  • Even if no packets are lost, and the channel maintains integrity, an overflow should never happen, and is a sign that something in the channel did not follow the specification
RO 0x0
15:12 err_overflow Per lane Dynamic Deskew Buffer overflow indicator
[n]=1: The dynamic deskew buffer for lane n overflowed sometime in the past since the last time it was reset
  • Once asserted, the value will hold until you clear it using the i_clear_internal_err port, or by resetting the RX datapath
  • The dynamic deskew buffer should be cleared by deasserting i_signal_ok, or by resetting the RX datapath
  • When a dynamic deskew buffer overflows, RX data is lost, which can cause packets to be lost, and frame errors
  • Even if no packets are lost, and the channel maintains integrity, an overflow should never happen, and is a sign that something in the channel did not follow the specification
RO 0x0
11:8 rd_numdata Per lane Dynamic Deskew Buffer Almost Full
[n]=1: The occupancy of the dynamic deskew buffer in lane n has exceeded the watermark set by rxpma_max_skew
  • Valid only for lanes actually in used by a multi-lane EHIP core
  • Exceeding the watermark doesn't indicate an error, but may be a sign that the a problem in the past is now limiting the amount of skew variation the core can tolerate
RO 0x0

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