E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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2.11.15. Miscellaneous Status and Debug Signals

The E-Tile Hard IP for Ethernet Intel FPGA IP provides a handful of status and debug signals to support visibility into the actions of the IP core and the stability of IP core output clocks.
Table 56.  Miscellaneous Status and Debug SignalsAll of the miscellaneous output status and debug signals except the i_stats_snapshot signal are asynchronous and must be synchronized before they are used. The signal names are standard with slight differences to indicate the variations. For example:
  • For variants with single 10GE/25GE channel: o_sl_tx_lanes_stable
  • For variants with more than 1 channel: o_sl_tx_lanes_stable[ch-1:0]
  • For variants with single 100GE channel: o_tx_lanes_stable

Signal

Width

Description

o_cdr_lock[n-1:0]

(n is the number of transceivers)

[n-1:0] Indicates that the recovered clocks are locked to data.

The o_clk_rec_div64[n] and o_clk_rec_div66[n] clocks are reliable only after o_cdr_lock[n] is asserted.

o_sl_tx_lanes_stable

o_sl_tx_lanes_stable[n-1:0]

o_tx_lanes_stable

1 Asserted when all physical TX lanes are stable and ready to transmit data for the corresponding Ethernet channel. Each channel has its own o_tx_lanes_stable.

o_sl_rx_block_lock

o_sl_rx_block_lock[n-1:0]

o_rx_block_lock

1 Asserted when the corresponding Ethernet channel completes 66-bit block boundary alignment on all PCS lanes. Each channel has its own block lock signal.

o_sl_rx_am_lock

o_sl_rx_am_lock[n-1:0]

o_rx_am_lock

1 Asserted when the RX PCS completes detection of alignment markers and deskew of the virtual PCS lanes in the corresponding Ethernet 100G channel.

o_sl_rx_pcs_ready

o_sl_rx_pcs_ready[n-1:0]

o_rx_pcs_ready

1 Asserted when the RX lanes of the corresponding Ethernet channel are fully aligned and ready to receive data.

o_sl_local_fault_status

o_sl_local_fault_status[n-1:0]

o_local_fault_status

1 Asserted when the RX MAC of the corresponding Ethernet channel detects a local fault: the RX PCS detected a problem that prevents it from receiving data. This signal is functional only if you set the Choose Link Fault generation option parameter to the value of Bidirectional or Unidirectional in the parameter editor or if you overwrite the parameter editor parameter by setting the link_fault_mode RTL parameter to the value of lf_bidir or lf_unidir.

o_sl_remote_fault_status

o_sl_remote_fault_status[n-1:0]

o_remote_fault_status

1 Asserted when the RX MAC of the corresponding Ethernet channel detects a remote fault: the remote link partner sent remote fault ordered sets indicating that it is unable to receive data. This signal is functional only if you set the Choose Link Fault generation option parameter to the value of Bidirectional in the parameter editor or if you overwrite the parameter editor parameter by setting the link_fault_mode RTL parameter to the value of lf_bidir.

i_sl_stats_snapshot

i_sl_stats_snapshot[n-1:0]

i_stats_snapshot

1 Directs the IP core to record a snapshot of the current state of the statistics registers. Assert this signal to perform the function of both the TX and RX statistics register shadow request fields at the same time, or to perform that function for multiple instances of the IP core simultaneously. Refer to TX Statistics Counters and RX Statistics Counters.

Assert the signal for the desired duration of the freeze of read values in the statistics counters. The rising edge sets the tx_shadow_on field (bit [1]) of the CNTR_TX_STATUS register at offset 0x846 and the rx_shadow_on field (bit [1]) of the CNTR_RX_STATUS register at offset 0x946. to the value of 1 and the falling edge resets these bits.

This signal is synchronous with the i_clk_tx clock.

o_sl_rx_hi_ber

o_sl_rx_hi_ber[n-1:0]

o_rx_hi_ber

1 Asserted to indicate the RX PCS of the corresponding Ethernet channel is in a HI BER state according to Figure 82-15 in the IEEE 802.3-2015 Standard. The IP core uses this signal in autonegotiation and link training.

o_sl_ehip_ready

o_sl_ehip_ready[n-1:0]

o_ehip_ready

1 The Ethernet channel deasserts this signal in response to an i_csr_rst_n or i_tx_rst_n reset, or either of the corresponding soft resets. After the reset process completes, the channel reasserts this signal to indicate that the Hard IP for Ethernet block has completed initialization and is ready to interoperate with the main Intel® Stratix® 10 die. While the o_ehip_ready signal is low, the channel's datapath is not ready for data on the client interface nor ready for register accesses on the Ethernet reconfiguration interface.

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