E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

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2.9. Functional Description

The E-Tile Hard IP for Ethernet Intel FPGA IP MAC+PCS variations implement an Ethernet MAC in accordance with the IEEE 802.3 Ethernet Standard. The IP core handles the frame encapsulation and flow of data between client logic and an Ethernet network through a 10-Gbps, 25-Gbps, and 100-Gbps Ethernet PHY implemented in hard IP, with optional Reed Solomon Forward Error Correction (RS-FEC).

In the transmit direction, the MAC accepts client frames, and inserts inter-packet gap (IPG), preamble, start of frame delimiter (SFD), padding, and CRC bits before passing them to the PHY. You can configure the MAC to accept some of the additions with the client frame. The MAC also updates the TX statistics counters. The PHY encodes the MAC frame as required for reliable transmission over the media to the remote end.

In the receive direction, the PHY passes frames to the MAC. The MAC accepts frames from the PHY, performs checks, updates statistics counters, strips out the CRC, preamble, and SFD, and passes the rest of the frame to the client. In RX preamble pass-through mode, the MAC passes on the preamble and SFD to the client instead of stripping them out. You can configure the MAC to provide the full RX frame at the client interface, the frame with CRC bytes removed, or the frame with CRC and RX PAD bytes removed.

The E-Tile Hard IP for Ethernet Intel FPGA IP also supports PCS Only, FlexE, and OTN variations. The PCS Only variations provide an MII interface to the client and transmit and receive Ethernet packets through a 10-Gbps, 25-Gbps, and 100-Gbps Ethernet PHY implemented in hard IP. The FlexE and OTN variations use PCS66 interface for transmitting and receiving 66b blocks, bypassing the MAC. The PCS Only, OTN , and FlexE variations support optional KR-FEC(528,514) or KP-FEC(544,514) for 25G and 100G Ethernet rate.

Figure 12. E-tile Architecture and Datapath OverviewShowing 12 out of 24 channels per tile.
Figure 13.  E-Tile Hard IP for Ethernet Intel FPGA IP Instance and Bypass Modes
Note: The E-Tile Hard IP for Ethernet Intel FPGA IP provides support for the OTN feature. For further inquiries, contact your nearest Intel sales representative.

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