Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

1.6.4. Wire-Level Connectivity

Wire-level connectivity enables you to manipulate wire-level connections in the system level view of Platform Designer. For example, you can enter a Verilog style syntax expression to drive an input port of an IP component. You can implement wire-level connectivity with the Platform Designer GUI or with the qsys-script utility.

After applying the expression, the port you specify moves from the current interface into a Wire-Level Endpoint interface. The new interface name appends _wirelevel to the existing interface name. If you remove the wire-level expression, the port restores to the original interface. However, not all interfaces are restorable to legal interfaces after certain ports change. Moving a port from its original interface might result in validation errors on the original interface.

After you move a port to a Wire-Level Endpoint interface, wire-level expressions must drive all bits in the vector. You cannot connect ports contained within this new interface type to any other interfaces.

The following general rules apply to wire-level expressions:

  • Wire-level connectivity is only available on optional input ports.
  • The wire-level expression can consist of input, output, and bi-directional ports, constant values, and logic terms using standard Verilog syntax.
  • Wire-level expressions can only consist of ports within the same level of hierarchy. If you require elements from a higher or lower hierarchy, you must export the appropriate elements to the same hierarchical context so that they are available for use in wire-level expressions at the same hierarchy level.
  • You can apply multiple expressions to a single input port unless they collide or cause bus contention.
  • You must resolve validation errors occurring on the original interface for the interface to function correctly.

Platform Designer validates the wire-level expressions and provides messages for syntax, port existence, and other systematic errors. This validation includes the following:

  • Validation of Verilog syntax.
  • Warning if any sub-operator elements don’t match bit size.
  • Warning if resulting combined bit size does not match the driven input port.
  • Validation that all module and port names exist.
  • Validation that all ports in a wire-level interface are input ports.
  • Validation that all wire-level expressions drive each input port within a wire-level interface.
  • Validation of no bus-contention, meaning that no one wire is driven by more than one expression.
  • In a composed _hw.tcl module, validation that all ports driven by wire-level expressions are not in any connection.
  • In a composed _hw.tcl module, validation that all ports driven by wire-level expressions are not exported.

After you define wire-level expressions for your system and resolve any errors, you next generate the system to create the Verilog files. When you apply the wire-level connections in the Platform Designer GUI, or with the qsys-script utility, the wire-level expression is inserts in the Verilog wrapper file that generates for your system. When you apply the wire-level connections with composed _hw.tcl commands, the wire-level expression inserts in the Verilog wrapper file that generates for the specified IP component.